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(→‎Pre-Patchings: Tabelle für Ein/Ausgänge und Pre-Patching korrigiert und doppelte Infos entfernt)
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== Pre-Patchings ==
== Ein-/Ausgänge mit Pre-Patchings ==


'''Oberer Teil:'''
'''Oberer Teil:'''
CLOCK:
CLK FM ->Clock Frequency
CLK PWM ->Clock Puls WM
CV LFO:
SPEED CV ->ROW B
LEVEL:
MIX IN ->ROW B
MULTI:
1 (über dem M) ->Clock
SLEW:
SLEW IN ->ROW A
S+H:
S+H IN ->PW LFO
TRIGGER ->Clock
DELAY:
DELAY IN ->Clock
LENGTH:
SEQ LENGTH ->16 Trigger/Gate input für Ende
'''Unterer Teil:'''
DIVIDER:
IN ->Gate (CL OUT)
MULTI:
1 (Links vom M) ->Clock
Q (Qunatizier):
1 QUA IN ->CH 1
2 QUA IN ->CH 2 (Bei 2x8)
Oberer Teil by Tomcat, versuch einer Table....:


{| class="wikitable"
{| class="wikitable"
|- class="hintergrundfarbe5"
|- class="hintergrundfarbe5"
! Buchse !! Art  !! Prepatched !! Beschreibung
! Modul !! Buchse !! Art  !! Pre-Patch !! Beschreibung
|-
| colspan="3" | CLOCK:
|-
|CLK FM || IN || || Clock Frequency
|-
|CLK PWM || IN || || Länge des Gates
|-
|EXT CLK || IN || || Externe Clock
|-
|RESE || IN || || Zurück auf Gate 1
|-
|PULSE || OUT || || Gate als Puls
|-
|-
|SQUARE || OUT || || Gate als Sägezahn
| Clock || CLK FM || IN || RAMP || Clock Frequency
|-
|-
|HOLD || IN || || Anhalten (Clock läuft weiter!)
| Clock || CLK PWM || IN || || Länge des Gates
|-
|-
| colspan="3" | GATE:
| Clock || EXT CLK || IN || || Externe Clock
|-
|-
|GATE 1 - 16 || OUT || || Einzelausgang pro Step
| Clock || RESET || IN || || Zurück auf Gate 1
|-
|-
| colspan="3" | PW LFO:
| Clock || PULSE || OUT || || Gate als Rechteck
|-
|-
|PULS || OUT || || Rechteck LFO
| Clock || SQUARE || OUT || || Gate als 50% Rechteck
|-
|-
|RAMP || OUT || || |\ LFO
| Clock || HOLD || IN || || Anhalten (Clock läuft weiter!)
|-
|-
|SYNC IN || IN ||  || Zum Synchronisieren
| Gate || GATE 1 - 16 || OUT ||  || Einzelausgang pro Step
|-
|-
| colspan="3" | CV LFO:
| PW LFO || PULSE || OUT ||  || Rechteck
|-
|-
|SQUARE || OUT || || Sägezahn LFO
| PW LFO || RAMP || OUT || CLK FM || Sägezahn/Triangle
|-
|-
|TRIANGLE || OUT ||  || /\ LFO
| PW LFO || SYNC IN || IN ||  || Zum Synchronisieren
|-
|-
|SPEED CV || IN || ROW B || Geschwindigkeit
| CV LFO || SQUARE || OUT || || 50% Rechteck
|-
|-
| colspan="3" | LEVEL:
| CV LFO || TRIANGLE || OUT ||  || Dreieck
|-
|-
|MIX IN || IN || ROW B   
| CV LFO || SPEED CV || IN || ROW B || Geschwindigkeit
|-
|-
|LEVEL OUT + || OUT         
| Level || MIX IN || IN || ROW B     
|-
|-
|LEVEL OUT - || OUT         
| Level || LEVEL OUT + || OUT         
|-´
| colspan="3" | MULTI:
|-
|-
|1 (über dem M) || IN || Clock     
| Level || LEVEL OUT - || OUT         
|-
|-
|2-3 || OUT       
| Multi || 1 (über dem M) || IN || Clock     
|-
|-
| colspan="3" | SLEW:
| Multi || 2-3 || OUT       
|-
|-
|SLEW IN || IN || ROW A   
| Slew || SLEW IN || IN || ROW A   
|-
|-
|RESET || IN        
| Slew || RESET || IN        
|-
|-
|SLEW OUT || OUT         
| Slew || SLEW OUT || OUT         
|-
|-
| colspan="3" | S+H:
| S&H || S+H IN || IN || PW LFO   
|-
|-
|S+H IN || IN || PW LFO   
| S&H || TRIGGER || IN || Clock     
|-
|-
|TRIGGER || IN || Clock     
| S&H || S+H OUT || OUT         
|-
|-
|S+H OUT || OUT         
| Trigger Delay || DELAY IN || IN || Clock      
|-
|-
| colspan="3" | DELAY:
| Trigger Delay || DELAY OUT || OUT       
|-
|-
|DELAY IN || IN || Clock    
| Length || SEQ TR OUT || OUT ||  || Rechteck LFO
|-
|-
|DEALY OUT || OUT       
| Length || SEQ LENGTH || IN || 16 || Trigger/Gate input für Sequenz-Ende
|-
|-
| colspan="3" | LENGTH:
| Sequencer Out || ROW A || OUT       
|-
|-
|SEQ TR OUT || OUT ||  || Rechteck LFO
| Sequencer Out || ROW B || OUT       
|-
|SEQ LENGTH || IN || 16 || Trigger/Gate input für Ende
|-
| colspan="3" | SEQ OUT:
|-
|ROW A || OUT       
|-
|ROW B || OUT       
|}
|}


Unterer Teil, Tabellenversuch:
'''Unterer Teil:'''


{| class="wikitable"
{| class="wikitable"
|- class="hintergrundfarbe5"
|- class="hintergrundfarbe5"
! Buchse !! Art  !! Prepatched !! Beschreibung
! Modul !! Buchse !! Art  !! Pre-Patched !! Beschreibung
|-
| colspan="3" | CLOCK+TRIGGER:
|-
| START || IN        
|-
| START/STOP || IN       
|-
| STEP || IN ||  || Next Step 1
|-
| RESET || IN ||  || Zurück auf Step 1
|-
| CL OUT || OUT ||  || Gate (1,2 oder 3)   
|-
| QT CLK OUT || OUT ||  || Quantizer  Gate   
|-
|-
| OUT BUS 1 || OUT || || Gate 1   
| Clock & Trigger || START || IN          
|-
|-
| OUT BUS 2 || OUT || || Gate 2   
| Clock & Trigger || START/STOP || IN       
|-
|-
| OUT BUS 3 || OUT  || || Gate 3   
| Clock & Trigger || STEP || IN || || Next Step 1
|-
|-
| colspan="3" | DIVIDER:
| Clock & Trigger || RESET || IN ||  || Zurück auf Step 1
|-
|-
| IN || IN ||  || Gate (CL OUT)   
| Clock & Trigger || CL OUT || OUT ||  || Gate (1,2 oder 3)     
|-
|-
| 1.n || OUT ||  || Jeder 2/4/8/16/32/64/128.
| Clock & Trigger || QT CLK OUT || OUT ||  || Quantizer  Gate   
|-
|-
| colspan="3" | MULTI:
| Clock & Trigger || OUT BUS 1 || OUT ||  || Gate 1   
|-
|-
| 1 (Links vom M) || IN ||  || Clock     
| Clock & Trigger || OUT BUS 2 || OUT ||  || Gate 2   
|-
|-
| 2-3 || OUT       
| Clock & Trigger || OUT BUS 3 || OUT  || || Gate 3     
|-
|-
| colspan="3" | MULTI:
| Divider || IN || IN ||  || Gate (CL OUT)   
|-
|-
| 1 - 4           
| Divider || 1.n || OUT ||  || Jeder 2/4/8/16/32/64/128.
|-
|-
| colspan="3" | Q (Qunatizier):
| Multi 1 || 1 (Links vom M) || IN || Clock   
|-
|-
| 1 QUA IN || IN || CH 1 || 1 Bei 1-16 und 1 Bei 2x8
| Multi 1 || 2-3 || OUT       
|-
|-
| 2 QUA IN || IN || CH 2 || (Bei 2x8)   2 Bei 2x8
| Multi 2 || 1 - 4             
|-
|-
| CV 1 QUA IN || IN || || Add to QUA 1    
| Quantizer || 1 QUA IN || IN || 1 CHA OUT || 1 Bei 1-16 und 1 Bei 2x8
|-
|-
| 1 QUA OUT || OUT        
| Quantizer || 2 QUA IN || IN || 2 CHA OUT || (Bei 2x8)   2 Bei 2x8
|-
|-
| 2 QUA OUT || OUT        
| Quantizer || CV 1 QUA IN || IN ||  || Add to QUA 1    
|-
|-
| colspan="3" | CL P1:
| Quantizer || 1 QUA OUT || OUT      
|-
|-
| FM CLK || IN || || Geschwindigkeit
| Quantizer || 2 QUA OUT || OUT      
|-
|-
| CLK PWM || IN || || Gate Länge
| CL P1 || FM CLK || IN || OUT BUS 1 || Geschwindigkeit
|-
|-
| OUT POS 1 || OUT ||  || Gate bei STEP 1|-
| CL P1 || CLK PWM || IN ||  || Gate Länge
|-
|-
| colspan="3" | CH:
| CL P1 || OUT POS 1 || OUT ||  || Gate bei STEP 1
|-
|-
| 1 CHA OUT || OUT ||  || CV 1-16 bzw. 1-8 Bei 2x8
| Channel Outs || 1 CHA OUT || OUT ||  || CV 1-16 bzw. 1-8 Bei 2x8
|-
|-
| 2 CHA OUT || OUT ||  || CV 1-16 bzw. 9-16 Bei 2x8
| Channel Outs || 2 CHA OUT || OUT ||  || CV 1-16 bzw. 9-16 Bei 2x8
|-
|-
| colspan="3" | I1:
| Inverter 1 || 1 INV IN || IN      
|-
|-
| 1 INV IN ||  || IN      
| Inverter 1 || 1 INV OUT || OUT  
|-
|-
| 1 INV OUT || OUT ||  || - INPUT?
| Inverter 2 || 2 INV IN || IN      
|-
|-
| colspan="3" | I2:
| Inverter 2 || 2 INV OUT || OUT
|-
|-
| 2 INV IN || IN        
| AND|| 1 AND IN || IN        
|-
|-
| 2 INV OUT || OUT ||  || - INPUT?
| AND || 2 AND IN || IN       
|-
|-
| colspan="3" | A:
| AND || AND OUT || OUT       
|-
|-
| 1 AND IN || IN        
| OR || 1 OR IN || IN        
|-
|-
| 2 AND IN || IN         
| OR || 2 OR IN || IN         
|-
|-
| AND OUT || OUT         
| OR || OR OUT || OUT         
|-
|-
| colspan="3" | O:
| XOR || 1 XOR IN || IN      
|-
|-
| 1 OR IN || IN        
| XOR || 2 XOR IN || IN         
|-
|-
| 2 OR IN || IN       
| XOR || XOR OUT || OUT
|-
| OR OUT || OUT       
|-
| colspan="3" | X:
|-
| 1 XOR IN || IN      
|-
| 2 XOR IN || IN       
|-
| XOR OUT || OUT
|}
|}
Noch ein paar Memos um das Chaos vorläufig zu komplettieren:
Zusatzinfos
1. Clock FM -> Bus 1
2. Clock Out -> Multiple (beide 3er Multiples, also jeweils mit der dazu gehörigen Clock)
3. PW LFO -> Clock FM
4. Quantizer vorgepatch (?)
Zusatz-Info: 2. Seq Reihe oben geht bis 10 V.


== Oberer Teil ==
== Oberer Teil ==

Version vom 20. September 2010, 18:02 Uhr

Ein-/Ausgänge mit Pre-Patchings

Oberer Teil:

Modul Buchse Art Pre-Patch Beschreibung
Clock CLK FM IN RAMP Clock Frequency
Clock CLK PWM IN Länge des Gates
Clock EXT CLK IN Externe Clock
Clock RESET IN Zurück auf Gate 1
Clock PULSE OUT Gate als Rechteck
Clock SQUARE OUT Gate als 50% Rechteck
Clock HOLD IN Anhalten (Clock läuft weiter!)
Gate GATE 1 - 16 OUT Einzelausgang pro Step
PW LFO PULSE OUT Rechteck
PW LFO RAMP OUT CLK FM Sägezahn/Triangle
PW LFO SYNC IN IN Zum Synchronisieren
CV LFO SQUARE OUT 50% Rechteck
CV LFO TRIANGLE OUT Dreieck
CV LFO SPEED CV IN ROW B Geschwindigkeit
Level MIX IN IN ROW B   
Level LEVEL OUT + OUT       
Level LEVEL OUT - OUT       
Multi 1 (über dem M) IN Clock   
Multi 2-3 OUT       
Slew SLEW IN IN ROW A   
Slew RESET IN      
Slew SLEW OUT OUT       
S&H S+H IN IN PW LFO   
S&H TRIGGER IN Clock   
S&H S+H OUT OUT       
Trigger Delay DELAY IN IN Clock    
Trigger Delay DELAY OUT OUT       
Length SEQ TR OUT OUT Rechteck LFO
Length SEQ LENGTH IN 16 Trigger/Gate input für Sequenz-Ende
Sequencer Out ROW A OUT       
Sequencer Out ROW B OUT     

Unterer Teil:

Modul Buchse Art Pre-Patched Beschreibung
Clock & Trigger START IN        
Clock & Trigger START/STOP IN       
Clock & Trigger STEP IN Next Step 1
Clock & Trigger RESET IN Zurück auf Step 1
Clock & Trigger CL OUT OUT Gate (1,2 oder 3)   
Clock & Trigger QT CLK OUT OUT Quantizer  Gate   
Clock & Trigger OUT BUS 1 OUT Gate 1   
Clock & Trigger OUT BUS 2 OUT Gate 2   
Clock & Trigger OUT BUS 3 OUT Gate 3   
Divider IN IN Gate (CL OUT)   
Divider 1.n OUT Jeder 2/4/8/16/32/64/128.
Multi 1 1 (Links vom M) IN Clock   
Multi 1 2-3 OUT       
Multi 2 1 - 4           
Quantizer 1 QUA IN IN 1 CHA OUT 1 Bei 1-16 und 1 Bei 2x8
Quantizer 2 QUA IN IN 2 CHA OUT (Bei 2x8)   2 Bei 2x8
Quantizer CV 1 QUA IN IN Add to QUA 1    
Quantizer 1 QUA OUT OUT      
Quantizer 2 QUA OUT OUT      
CL P1 FM CLK IN OUT BUS 1 Geschwindigkeit
CL P1 CLK PWM IN Gate Länge
CL P1 OUT POS 1 OUT Gate bei STEP 1
Channel Outs 1 CHA OUT OUT CV 1-16 bzw. 1-8 Bei 2x8
Channel Outs 2 CHA OUT OUT CV 1-16 bzw. 9-16 Bei 2x8
Inverter 1 1 INV IN IN      
Inverter 1 1 INV OUT OUT
Inverter 2 2 INV IN IN      
Inverter 2 2 INV OUT OUT
AND 1 AND IN IN      
AND 2 AND IN IN       
AND AND OUT OUT       
OR 1 OR IN IN      
OR 2 OR IN IN       
OR OR OUT OUT       
XOR 1 XOR IN IN      
XOR 2 XOR IN IN       
XOR XOR OUT OUT

Oberer Teil

Anzahl Schritte setzen

Entweder den Gate-Ausgang mit Reset-In verbinden oder mit dem Seq Length Eingang. Beim Reset-Eingang muss man allerdings das Folge-Gate benutzen (2 Schritte = Gate 3 mit Reset-In verbinden, statt Gate 2).